--******************************************************************************
-- File: main_vhdl.vhd
-- Author: Matthew Hosking
-- Created: 09/01/2009
-- Description: A high level file to show the connections necessary between
--				various components (both VHDL & Verilog) used for the VGA driver.
--
--******************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main_vhdl is
	PORT(	SIGNAL SYSTEM_CLOCK					: IN std_logic;
			SIGNAL SW1, SW2, SW3, SW4			: IN std_logic;              
			SIGNAL VGA_OUT_RED					: OUT std_logic_vector(7 downto 0);
			SIGNAL VGA_OUT_GREEN					: OUT std_logic_vector(7 downto 0);
			SIGNAL VGA_OUT_BLUE 					: OUT std_logic_vector(7 downto 0);
			SIGNAL VGA_HSYNCH,VGA_VSYNCH		: OUT std_logic;
			SIGNAL VGA_COMP_SYNCH				: OUT std_logic;
			SIGNAL VGA_OUT_BLANK_Z				: OUT std_logic;
			SIGNAL VGA_OUT_PIXEL_CLOCK			: OUT std_logic;
			SIGNAL keyboard_clk 						: IN std_logic;
			SIGNAL keyboard_data 					: IN std_logic;
			SIGNAL led_l,led_r,led_u,led_d	: OUT std_logic);
end main_vhdl;

--******************************************************************************
-- Architecture topRow
--****************************************************************************** 
architecture struct of main_vhdl is
	
	--*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
	-- Declare VERILOG modules as VHDL components
	--		Syntax is very important, Verilog is case sensitive!
	--*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

	----------------------------------------------------------
	-- CLOCK_GEN.v
	----------------------------------------------------------
	component CLOCK_GEN is
		port( 
			SYSTEM_CLOCK					: in std_logic;	-- 100MHz LVTTL SYSTEM CLOCK
			system_clock_buffered		: out std_logic;	-- buffered SYSTEM_CLOCK
			pixel_clock						: out std_logic;	-- SYSTEM_CLOCK / 4
			reset								: out std_logic	-- reset asserted when DCMs are NOT LOCKED
		);
	end component;	
	----------------------------------------------------------
	-- SVGA_TIMING_GENERATION.v
	----------------------------------------------------------
	component SVGA_TIMING_GENERATION is
		port( 
			pixel_clock						: in std_logic;
			reset								: in std_logic;
			h_synch_delay					: out std_logic;	-- horizontal synch for VGA connector
			v_synch_delay					: out std_logic;	-- vertical synch for VGA connector
			comp_synch						: out std_logic;	-- composite synch for DAC
			blank								: out std_logic;	-- composite blanking
			pixel_count						: out std_logic_vector(10 downto 0); 	-- counts the pixels in a line
			line_count						: out std_logic_vector(9 downto 0) 		-- counts the display lines
		);
	end component;	
	----------------------------------------------------------
	-- VIDEO_OUT.v
	----------------------------------------------------------
	component VIDEO_OUT is
		port( 
			pixel_clock						: in std_logic;
			reset								: in std_logic;
			vga_red_data					: in std_logic_vector(7 downto 0);
			vga_green_data					: in std_logic_vector(7 downto 0);
			vga_blue_data					: in std_logic_vector(7 downto 0);
			h_synch							: in std_logic;
			v_synch							: in std_logic;
			comp_synch						: in std_logic;
			blank								: in std_logic;
			VGA_OUT_PIXEL_CLOCK			: out std_logic;
			VGA_HSYNCH						: out std_logic;
			VGA_VSYNCH						: out std_logic;
			VGA_COMP_SYNCH					: out std_logic;
			VGA_OUT_BLANK_Z				: out std_logic;
			VGA_OUT_RED						: out std_logic_vector(7 downto 0);
			VGA_OUT_GREEN					: out std_logic_vector(7 downto 0);
			VGA_OUT_BLUE					: out std_logic_vector(7 downto 0)
		);
	end component;
	----------------------------------------------------------
	-- xilinx_ball.vhdl
	----------------------------------------------------------
	component xilinx_ball IS
		PORT(
			SIGNAL PB1, PB2				: IN std_logic;
			SIGNAL pixel_clock			: IN std_logic;
			SIGNAL reset					: IN std_logic;
			SIGNAL pixel_count0			: IN std_logic_vector(10 downto 0);
			SIGNAL line_count0			: IN std_logic_vector(9 downto 0);
			SIGNAL vga_red_data			: OUT std_logic_vector(7 downto 0);
			SIGNAL vga_green_data		: OUT std_logic_vector(7 downto 0);
			SIGNAL vga_blue_data			: OUT std_logic_vector(7 downto 0);
			SIGNAL keyboard_clk 						: IN std_logic;
			SIGNAL keyboard_data 					: IN std_logic;
			SIGNAL clock_100Mhz	 					: IN std_logic;
			SIGNAL led_l, led_r, led_u, led_d	: OUT std_logic;
			SIGNAL inp									: IN std_logic

		);
	end component;
	----------------------------------------------------------
	-- xilinx_ball_x.vhdl
	----------------------------------------------------------
	component xilinx_ball_x IS
		PORT(
			SIGNAL PB1, PB2				: IN std_logic;
			SIGNAL pixel_clock			: IN std_logic;
			SIGNAL reset					: IN std_logic;
			SIGNAL pixel_count0			: IN std_logic_vector(10 downto 0);
			SIGNAL line_count0			: IN std_logic_vector(9 downto 0);
			SIGNAL vga_red_data			: OUT std_logic_vector(7 downto 0);
			SIGNAL vga_green_data		: OUT std_logic_vector(7 downto 0);
			SIGNAL vga_blue_data			: OUT std_logic_vector(7 downto 0);
			SIGNAL keyboard_clk 						: IN std_logic;
			SIGNAL keyboard_data 					: IN std_logic;
			SIGNAL clock_100Mhz	 					: IN std_logic;
			SIGNAL led_l, led_r, led_u, led_d	: OUT std_logic;
			SIGNAL inp									: IN std_logic
		);
	end component;
	

	-- signals to connect components
	signal s_pixel_clock			: std_logic;
	signal s_reset					: std_logic;
	signal s_h_synch_delay		: std_logic;
	signal s_v_synch_delay		: std_logic;
	signal s_comp_synch			: std_logic;
	signal s_blank					: std_logic;
	signal s_pixel_count			: std_logic_vector(10 downto 0);
	signal s_line_count			: std_logic_vector(9 downto 0);
	SIGNAL 	clock_buf: std_logic;
	signal s_vga_red_data		: std_logic_vector(7 downto 0);
	signal s_vga_green_data		: std_logic_vector(7 downto 0);
	signal s_vga_blue_data		: std_logic_vector(7 downto 0);
	
begin
	--------------------------------------------------------
	-- PORT MAP CLOCK_GEN
	--------------------------------------------------------
   cg : CLOCK_GEN
 		PORT MAP(
			SYSTEM_CLOCK					=>	SYSTEM_CLOCK,
			system_clock_buffered		=> clock_buf,
			pixel_clock						=> s_pixel_clock,
			reset								=> s_reset
		);
	--------------------------------------------------------
	-- PORT MAP SVGA_TIMING_GENERATION
	--------------------------------------------------------
	svga_t_gen : SVGA_TIMING_GENERATION
 		PORT MAP(
			pixel_clock						=> s_pixel_clock,
			reset								=> s_reset,
			h_synch_delay					=> s_h_synch_delay,
			v_synch_delay					=> s_v_synch_delay,
			comp_synch						=> s_comp_synch,
			blank								=> s_blank,
			pixel_count						=> s_pixel_count,
			line_count						=> s_line_count
		);
	--------------------------------------------------------
	-- PORT MAP VIDEO_OUT
	--------------------------------------------------------
	vid_out : VIDEO_OUT
 		PORT MAP(
			pixel_clock						=> s_pixel_clock,
			reset								=> s_reset,
			vga_red_data					=> s_vga_red_data,
			vga_green_data					=> s_vga_green_data,
			vga_blue_data					=> s_vga_blue_data,
			h_synch							=> s_h_synch_delay,
			v_synch							=> s_v_synch_delay,
			comp_synch						=> s_comp_synch,
			blank								=> s_blank,
			VGA_OUT_PIXEL_CLOCK			=> VGA_OUT_PIXEL_CLOCK,
			VGA_HSYNCH						=> VGA_HSYNCH,
			VGA_VSYNCH						=> VGA_VSYNCH,
			VGA_COMP_SYNCH					=> VGA_COMP_SYNCH,
			VGA_OUT_BLANK_Z				=> VGA_OUT_BLANK_Z,
			VGA_OUT_RED						=> VGA_OUT_RED,
			VGA_OUT_GREEN					=> VGA_OUT_GREEN,
			VGA_OUT_BLUE					=> VGA_OUT_BLUE
		);
	--------------------------------------------------------
	-- PORT MAP xilinx_ball
	--------------------------------------------------------
	x_ball_y : xilinx_ball
	--x_ball_x : xilinx_ball_x
		PORT MAP(
			PB1					=> '0', 
			PB2					=> '0',
			pixel_clock			=> s_pixel_clock,
			reset					=> s_reset,
			pixel_count0		=> s_pixel_count,
			line_count0			=> s_line_count,
			vga_red_data		=> s_vga_red_data,
			vga_green_data		=> s_vga_green_data,
			vga_blue_data		=> s_vga_blue_data,
			keyboard_clk		=>  keyboard_clk,
			keyboard_data 		=>	 keyboard_data,
			clock_100Mhz	 	=>	 clock_buf,
			led_l       		=>  led_l,
			led_r       		=>  led_r,
			led_u       		=>  led_u,
			led_d	      		=>  led_d,
			inp					=>  SW1
		);
end struct;